This disclosure generally relates to computer hardware testing and development, and more specifically relates to a system and method for list insertion of test segments with non-naturally aligned data boundaries into a processor memory.
Processor testing tools attempt to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be able to stress various timing scenarios and operations on the processor, including the coherency of cache memory. Coherency in the cache memory involves insuring that changes to data in the cache are accurately reflected to main memory to keep the data consistent. Building test cases to thoroughly test a processor can be extremely costly in time and resources, thus building efficient test cases is an important goal of processor testing.
Many processors have restrictions on alignment for memory operations. For example, some Power processors allow different alignment boundaries in memory for different instructions while in different modes like Cache Inhibited, Little Endian etc. With these complexities on boundary restrictions, it's very difficult to generate test cases for the different alignment boundaries for each of the instructions. Moreover, testing all valid boundaries for an instruction is very important and multiple test cases for multiple boundaries would have the overhead of generation and simulation in case of reference model checking. Test case generation can be extremely labor intensive to test the different alignment boundaries while preserving boundaries where needed.